Processor Design Project
This is the homepage for the Processor Design Project. You can find most course information here.
This course is part of the CESE masters programme. This course is a continuation of the curriculum of Computer Engineering (CESE4130) and Modern Computer Architecture (CESE4085).
Notice of Changes
This course will be SIGNIFICANTLY changed this year (2025), and the information on this page is no longer 100% correct. It is currently being updated.
Project Overview
- You do this project in groups of four (4) students
- You can form your own groups using Brightspace
- Every group will be provided with login credentials for the Design Server
In this course, you will be enhancing an RISCV-based CPU and its associated LLVM toolchain for the task of Advanced Encryption Standard (AES) encoding in groups of four (4). First, you will extend the basic CPU (named RISCY) with your own implementation of the AES instructions, aes32esi and aes32esmi. Thereafter, you will implement a LLVM loop unrolling pass for the aes32esmi instruction. All additional improvements and optimisations of the AES enhanced RISCY CPU and LLVM compiler are up to your group. Please remember that you have to evaluate your new design for the intended improvements and quantitatively compare against a state-of-the-art baseline. Your designs will be targeting an FPGA board. To facilitate you doing so, you will receive:
- A git repository which includes the basic RISCV processor (RISCY) VERILOG code, the LLVM source files and a simple benchmark (A software implementation of AES).
- All necessary tools and files required for simulation and FPGA implementation are available on a design server.
- This website, detailing the project assignment and the simulation general flow and toolset.
Schedule
| Date | Activity |
|---|---|
| April 23rd in Pulse Hall 10 | Kickoff Meeting at 13:45 |
| Every Thursday afternoon (except public holidays) | Q&A Lab in EWI Halls H,G,K,L and M from 13:45 to 17.45 |
| May 2 | Intermediate Report Submission |
| May 9 | Feedback on your Intermediate Report |
| June 20 | Final Report and Project Submission |
| TBD | (TBD Project Presentation) |
Getting Started
- Form a Group of four student and register it in Brightspace!
- Carefully read the First Phase section. It contains information on what is expected in the first two weeks of the project.
- Any additional questions on how to set up your project, and other support will be provided at the weekly labs!
* In Platform description describes the MIPS processor you will be modifying in this project. - In Frequently Asked Questions we are collecting some frequent questions. Please contribute in the labs! (NEED UPDATE)
Grading Procedure
The projects functionality will be verified and checked for (including between groups) plagiarism.
If the project is not functional you DO NOT pass the course. Plagiarism can also make you fail.
The final score for the project is determined based on the following criteria:
The evaluation method and criteria are changed this year (2025)! Soon, the new rules will be available.