Frequently Asked Questions

Can somebody take a look at my design? I have some errors that I do not manage to solve.

No, we cannot debug your VHDL programs for you. There are weekly labs in which you can ask questions about technical issues you're facing. However, we generally expect you to debug your own code. We can recommend using version control software to keep track of old versions of your code such that you can go back to it.

Can I have a discussion with you about the design? I have some ideas to improve it.

Yes. There are weekly labs, and there is an intermediate milestone meeting scheduled on May 9th or 10th in which those things can be discussed. Prior and after that, you may email your questions to j.b.doenszelmann@tudelft.nl and/or S.D.Cotofana@tudelft.nl.

One-time path updating for Vitis the first time you launch the tool.

Right click on design_2_wrapper in the Explorer pane, select Build Project. Then right click on design_2_wrapper in the Explorer pane, select Update Hardware Specification, browse and select the .xsa file that you just exported from Vivado (folder fpga/zynq_fpga/workspace).

ERROR in Vitis: Cannot find -lxil.

Right click on the appARMcpu in the Explorer pane, Properties, C/C++ General, Paths and Symbols, Library Paths, and add the path of libxil.a

Simulation gets stuck at the Execute Simulation step.

Add the pdp folder to the exception list for scanning by the antivirus software installed on own computer.