Second Phase of the PDP project

In weeks 3 to 8 you will work on two different sets of tasks where the first task is common for all groups.

Task 1

In this task, you will implement standard AES encryption instructions, aes32esi and aes32esmi, in Verilog and integrate with RISCY, known as hardware implementation. On the other side, known as software imeplementation, you modify the software AES code to use the assembly instructions along with the built-in loop-unrolling pass of LLVM for the AES inner round instruction (aes32esmi). You are also expected to evaluate the advantages of the above improvements as compared to the unmodified RISCY core running the AES in software. All of these tasks should be completed before proceeding to the second set of tasks. Briefly, the steps are:

1. Implement instructions in Verilog.
2. Modify the C code to use aes32esmi and aes32esi.
3. Obtain the IR representation of the code and verify that assembly instructions are used properly.
4. Apply the LLVM loop-unroll optimization pass to the modified code and verify that the loop has been unrolled.

Please note that hardware and software implementations can be done in parallel by group memebers, however, we recommend you to synchronize yout findings.

The description of the instructions can be found in ZKNE manual. The manual explains how the instructions work and how they should be used. Since the description and general usage of instructions are similar, we only explain the details of the middle round instruction. The format of aes32esmi looks like:

aes32esmi rd, rs1, rs2, bs

Where

• rd: Destination register
• rs1 and rs2: Source registers
• bs: Byte shift value

To be able to use the assembly instruction in the C code, __asm__ directive is used as shown below:

__asm__ volatile (
       "aes32esmi %0, %1, %2, %3"
         : "+r" (X1)
         : "r" (X2),
           "r" (X3),
           "I" (X4)
);

Where %0, %1, %2, and %3 are corresponding to rd, rs1, rs2, and bs, respectively. Please note that you have to complete the instruction by properly filling X1...X4.

To verify that the modified code, you can quickly compile and execute the code and compare the output (encrypted text) with the software implementation code. Since the input and key are hardcoded in the source file, it is expected to get a single unique output.

Once you have verified that the assembly instructions are functionally correct, you can proceed with LLVM optimization passes. Here, we focus on the loop-unroll pass on the initial IR representation, so the effect would be the unrolled middle round of AES encryption. While there are several passes overlapping functions, it is mandatory to apply loop-unroll and get the final correct result. To check if the loop has been unrolled, you should first count the number of aes32esmi instructions inside the original loop and then multiply that by the number of iterations, fixed 9 times. The same number of instructions must be observed in the unrolled version.

Task 2

The second set of tasks is aimed to implement, debug and validate the group specific system improvements. Generally, each group has to propose an idea and hypothesis in the intermediate report. The confirmation and feedback is given TA team. Please note that this part will be completely different for each team as well as the reference baseline for comparison (aka state-of-the-art) that will be used for validating the implemented improvements.