4 FPGA Board

4.1 Setup

This project uses the PYNQ-Z1 Board from Digilent. It has the ZYNC-7000 SoC device from AMD (formerly Xilinx) with a hardened ARM Cortex-A9 core directly connected to the Programmable Logic (PL). The communication with the board will be done via ethernet cable, which will be used to run Jupyter Notebooks in the processing system (ARM core). To be able to do this, the board needs to be set up as shown in Figure 15. For more information, see the board manual.
Figure 15. PYNZ-Z1 board

Follow the steps below:

  1. Set the JP4 / Boot jumper to the SD position by placing the jumper over the top two pins of JP4. This sets the board to boot from the Micro-SD card.
  2. To power the PYNQ-Z1 from the micro USB cable, set the JP5 / Power jumper to the USB position. You can also power the board from an external 12V power regulator by setting the jumper to REG.
  3. Insert the Micro SD card loaded with the PYNQ-Z1 image into the Micro SD card slot underneath the board.
  4. Connect the USB cable to your PC/Laptop, and to the PROG - UART / J14 MicroUSB port on the board.
  5. Connect the board to Ethernet by following the instructions below.
  6. Turn on the PYNQ-Z1 and check the boot sequence (explained below).

Boot sequence:

  1. Slide the power switch to the ON position to turn on the board. The Red LD13 LED will come on immediately to confirm that the board has power. After a few seconds, the Yellow/Green LD12 / Done LED will light up (green) to show that the ZYNC device is operational.

  2. After a minute you should see two Blue LD4 & LD5 LEDs and four Yellow/Green LD0-LD3 LEDs flash simultaneously. The Blue LD4-LD5 LEDs will then turn on and off while the Yellow/Green LD0-LD3 LEDs remain on. The system is now booted and ready for use.

  3. Connect the FPGA board to a computer:
    You need a computer with a free Ethernet port [^1]1.
    You also need to have the permissions to configure your network interface.
    With a direct connection, you are able to use PYNQ.

Follow the steps below to connect directly to a computer using static IP2 address:

  1. Assign a static IP address (how to).
  2. Connect the board to your computer’s Ethernet port.
  3. Open a web browser and browse to http://192.168.2.99.
  4. The credentials to login on the web page are xilinx/xilinx.
3

If you don’t have the cable, you may ask for it in the weekly meetings.

1

If your laptop has no Ethernet port, you need an Ethernet-to-USB converter. You may ask for it in the weekly meetings.

2

Here, IP refers to Internet Protocol and not Intellectual Property.

4.2 Running on FPGA

Once logged in, the main screen of the Jupyter notebook is similar to Figure 16. If you are not familiar with Jupyter notebook, you may want to check this tutorial.
Figure 16. Jupyter notebook web page

The content of the folder riscy is shown in Figure 17.
Figure 17. Folder content

Inside mem_files you see data.coe and code.coe, which are the memory initialization files for the BRAMs connected to the RISCY core. The overlays directory contains the following:

  • base_riscy.bit: Generated bitstream from the main riscy project, can be found in pdp-project/hardware/vivado/riscy/riscy.runs/impl_1/riscv_wrapper.bit.
  • base_riscy.tcl: Generated at the same time as the bitstream, you can find it in pdp-project/hardware/vivado/riscy/riscy.runs/impl_1/riscv_wrapper.tcl.
  • base_riscy.hwh: Hardware handoff file, autogenerated from the riscy project in pdp-project/hardware/vivado/riscy/riscy.gen/sources_1/bd/riscv/hw_handoff/riscv.hwh.

These 3 files will have different names when you generate them using Vivado. Then you should rename them to the same to be able to use them in the Jupyter Notebook and the name should match that of the bitstream when importing it with the Overlay command inside the Jupyter notebook.

You can find a copy of this base directory in pdp-project/hardware/sw/fpga/riscy.

With all the files available and accessible via the browser in the FPGA, you can now proceed to run the base_riscy.ipynb notebook. This notebook contains the code and explanations to perform the following actions:

  1. Initialize the notebook, load the overlay (PL image/bitstream) and some helper functions to initialize the BRAMs.
  2. Program the PL with the bitstream.
  3. Control the RISCY core by performing AXI writes/reads to the riscv_control module.
  4. Programming the instruction and data memories.
  5. Read the instruction and data memories.
  6. Start/stop the fetching from the core.
  7. Check the results written by the core to memories or the duration of the test registered by the mem_snoop module.