Project Submission

The project submission must be done via e-mail.

In your final submission, you should include:

  • The report – preferably a pdf - (naming convention: CESE4040_2023_report_g#, with # being the group number) in the root of your git repository. See Reporting
  • Your git repository (ONLY the main branch counts)

The report should include the following:

  1. The general idea behind you overall optimization proposal. Related to the parts that you decided to change or to append you must answer (at least) these questions: What, how, and why?
  2. The design of the improved and/or appended part(s). There is no need to go at the gate level! The basic algorithm you decided to implement, and the RTL designs are in general enough. In case some parts are relevant you may go to full adder/gate level if this is essential for your proposal.
  3. Performance results for the baseline design (the original MIPS system) and your improved core. Those should include the following: Detailed implementation results including timing information, critical path information, resource utilization information from Vivado report, and power consumption figures.
  4. A comparison between your design and the baseline design in terms of basic metrics, i.e., Area (A), critical path Delay (deduced from clock frequency) (D), Benchmarks Score in terms of execution clock cycles (BS), maximum Power (P), total Energy consumption (E), as well as compound metrics, e.g., , , and products.
  5. Comments on the obtained results, e.g., answer to “Which improvement is mostly contributing to each figure of merit?”.
  6. Conclusions.

The report may also include, but it is not mandatory, suggestions for this project! Your feedback is very much appreciated. If you want to do so anonymously, you're also invited to fill in the Evasys questionaire after the course is over.