Vivado Project Setup

Creating a Project

To generate a new project in Vivado follow the steps:

  1. Download the Board files from here and paste them into {installation_location}\Xilinx\Vivado\2023.2\data\boards\board_files\
  2. Start Vivado, Select Create Project
  3. Name your project and select Next
  4. Select RTL Project and ensure, Do not specify sources at this time is selected
  5. Select Boards and search for PYNQ-Z1; Select the board from the list and click Next
  6. Click Finish and your project is completed

Setting up a Project

First you need to add the constraints file for the selected board. For the PYNQ-Z1 board follow the following steps:

  1. Add the constraints file for the board from the template repo, PYNQ-Z1_Constraints.xdc. Press the + button in the Sources Tab or Press ALT+A
  2. Select Add or create constraints, add the file downloaded in the previous step, and select Finish
  3. The constraint file has all the available GPIOs, LEDs, Buttons, and Switches on the board. You need to uncomment the ones you will need for the project.
  4. PYNQ-Z1 also provides a 125MHz clock, enable it and use it in your design.

Second, you will have to either add or create a new source file. This can done similarly to the constraint file but by selecting, Add or create sources. A source file is an Verilog file, in which you write your code. Ensure that the inputs and outputs of the Verilog module are set correctly.

Third, you will have to create a new block diagram. Block Diagram is used to stitch different IPs and components together in your project. To create a block diagram select Flow Navigator -> IP Integrator -> Create Block Diagram. You can now add your Verilog source to this block diagram by right-clicking on the file and selecting Add Module to Block Diagram. If you want to connect any pins from your block to external GPIOs, you can right-click on them and select Make External or press Cntr + T.

Ensure that the names of the resources in the constraint file and the block diagram are the same.

Fourth, and finally, once your block diagram is completed Right-click on it and select Create HDL Wrapper.... This will make an additional Verilog file which will act as the top layer of your project connecting all the IPs and sources in the block diagram together.

Now the project can be simulated or bitstream can be generated.