Simulation

In this section, we explain the provided simulation and testbench setup, and how to use it. Since this is a complicated project, we provide you with a working testbench. It is assumed that you are familiar with Vivado Simulations, if not please refer to: Lab 1 Simulation & Synthesis.

The provided testbench.v consists of two main components

• picorv32 module: The core as a Unit Under Test
• memory module: A custom memory module for the core. RISC-V machine code (instructions) can be loaded into this memory.

Simulation programs

To simulate your core, you need a set of instructions for the core to execute (obviously). In the template, this is achieved by loading the memory module with RISC-V Machine code. There are two programs provided in the template, memory_data.mem which is compiled using Baseline ISA, and mod_memory.mem which is compiled with the new instruction (Modified ISA).

Choosing a program

Before simulating you need to select which program you want to simulate. This can be done by uncommenting one of the $readmemh instructions, as shown below.

56
57    // Baseline ISA
58    $readmemh("memory_data.mem", mem.memory_array);
59    
60    // Modified ISA
61    //$readmemh("mod_memory.mem", mem.memory_array);
62

To ensure that your simulation is executing correctly, validate your results against Expected Simulation Output bellow.

Expected Simulation Output

Both the simulation codes perform the same operations. Verify that the final output Matches the following

When the register values match with the table above, that means the simulation has run successfully.