Project Structure

In this section, we explain how the RISC-V PicoRV32 core is implemented in the PYNQ Z-1 FPGA Board.

Block Diagram

The block diagram is a high-level design for all the components implemented on the FPGA.

High-Level Components

  • system_reset: Reset the complete FPGA
  • picorv32_reset: Reset only the RISC-V core
  • ZYNQ Processing Systems: A hardwired ARM core within the FPGA. It is used to program and validate the RISC-V Core.
  • picorv32_processor: RISC-V Core
  • memory_block: Contains the Instruction (ROM) and Data (RAM) for the RISC-V core
  • processor_interconnects: Used to connect the 2 cores with the memory and external GPIOs

How a Program runs on the RISC-V Core

The hardwired ARM core is used to interact with the RISC-V core. Following are the steps to run and validate a program on the RISC-V core.

  1. The FPGA is initialized and all the memory blocks are reset
  2. The ARM core loads the instruction and data memory with RISC-V machine code
  3. The RISC-V core is reset and executes the program according to the instructions in the instruction memory
  4. The ARM core waits till the RISC-V core is finished execution.
  5. The ARM core validates the output of the RISC-V core, which is stored at a pre-defined address in the data memory.
  6. A green LED indicates successful execution, a red LED indicates a failed execution.

Note: Red_LD5 is connected to PicoRV32 trap signal. A trap is triggered when an incorrect instruction is read or the processor is in a deadlock situation.