Additional resources

Any additional resources regarding lectures and labs can be found on this page. They will be added throughout the duration of the course.

Lab 1: Introduction to Vivado / Verilog

Lab 2: RISC-V

RISC-V Register Map

5-bit Encoding (rx)RegisterABI NameDescription
0 (0b00000)x0zerohardwired zero
1 (0b00001)x1rareturn address
2 (0b00010)x2spstack pointer
3 (0b00011)x3gpglobal pointer
4 (0b00100)x4tpthread pointer
5 (0b00101)x5t0temporary register 0
6 (0b00110)x6t1temporary register 1
7 (0b00111)x7t2temporary register 2
8 (0b01000)x8s0saved register 0
9 (0b01001)x9s1saved register 1
10 (0b01010)x10a0function argument 0
11 (0b01011)x11a1function argument 1
12 (0b01100)x12a2function argument 2
13 (0b01101)x13a3function argument 3
14 (0b01110)x14a4function argument 4
15 (0b01111)x15a5function argument 5
16 (0b10000)x16a6function argument 6
17 (0b10001)x17a7function argument 7
18 (0b10010)x18s2saved register 2
19 (0b10011)x19s3saved register 3
20 (0b10100)x20s4saved register 4
21 (0b10101)x21s5saved register 5
22 (0b10110)x22s6saved register 6
23 (0b10111)x23s7saved register 7
24 (0b11000)x24s8saved register 8
25 (0b11001)x25s9saved register 9
26 (0b11010)x26s10saved register 10
27 (0b11011)x27s11saved register 11
28 (0b11100)x28t3temporary register 3
29 (0b11101)x29t4temporary register 4
30 (0b11110)x30t5temporary register 5
31 (0b11111)x31t6temporary register 6

Area Utilization

To open the area utilization report follow the following steps:

  1. Ensure that you have a Generated Bitstream
  2. Open Implemented Design, select this above the Generate Bitstream
  3. Select Report Utilization
  4. Navigate till you see the picorv32_0

The steps are highlighted below in the picture:

Area Steps

Using the Desktop

Your group can use the desktops in the labs to generate the bitstream. However, some of the desktops cannot be used to program the FPGA. If you need to use the desktops, come to the front of the room, where te first two rows of computers should support programming the FPGA.

To use the desktop follow the steps:

  1. Login with your NetID and password
  2. Download the part files from here: No longer available
  1. Extract the file into C:\Programs\Xilinx2023.2\Vivado\2023.2\data\parts\xilinx
  2. You can start Vivado and open the template project
    • Make sure that you do not get any warnings when you open the template. If you get any errors please contact a TA

Flashing FPGA from the Desktop

The Desktop PCs do not have Vitis CLassic Installed on them. Thus you will be using a custom python script to flash the FPGAs. The script can be downloaded from here: Auto_Upload_Script.

To use the script, follow the steps:

  1. Unzip the script
  2. Replace the design_1_wrapper.bit with your generated bitstream
  3. Double-click on run_script.py to execute the script

Ensure that you open a Serial Port before running the script

Running Remotely

For groups that cannot upload the program onto the FPGA, please upload your Exported Hardware file (*.xsa) to your groups OneDrive folder here: No longer available

Once uploaded there will be TA laptops placed at the front of the Lab for you to upload your program from.

Note: This can be a bottle-neck if many groups want to test their design at the same time. So please keep that in mind and work efficiently. Such as using the desktops in front of the class.

Lab 3: CUDA

Template download

Download the template used for lab 3 here: lab3-cuda-template

List of useful commands on DelftBlue

  • See your if your job sits in the queue: squeue -u $USER
  • See the job queue: squeue

Lab 4: GVSoC

Extra resources