Milestone Meeting

The milestone meeting is in person and per group, and it is meant to be a midterm status check. It is NOT optional!

For the milestone meeting you must:

  1. Get familiarized with the project set-up and the FPGA server.
  2. Carry on the performance evaluation of the base-line processor design on the FPGA board with the provided benchmark suite.
  3. Make use of Vivado synthesis and implementation options to optimize the base-line performance without operating any changes on the SoC design (except increasing the clock frequency if the slack allows for it) and redo the FPGA evaluation.
  4. Perform a Cache Design Space Exploration (DSE). The baseline design includes a 2KB direct mapped cache, which only maps the first 2MB of the main memory. However, the cache design is parametric thus during the DSE process you may vary the cache size, the amount of main memory mapped in the cache, the cache line width, and cache associativity. Moreover, you can also operate other changes on the cache, e.g., change the replacement policy in case of associative caches. During the DSE you need to evaluate the clock frequency, execution cycles, area, and energy consumption of all the considered cache configurations and determine the most effective one, according with your own design goal.
  5. Identify at least two more possible improvement avenues.

For the milestone meeting you are required to present a short progress report that:

  1. Provides an overview of the Vivado optimization settings and comments on their impact on platform performance.
  2. Describes and comments on the impact of memory hierarchy changes on the platform performance.
  3. Presents the improvement approach that you decided to follow (justify your choices), the expected performance improvement, and the work status (up to date achievements)